| 时延驱动的VLSI版图规划算法 |
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| 引用本文： | 戚肖宁,冯之雁.时延驱动的VLSI版图规划算法[J].电子学报,1995,23(2):103-105. |
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| 作者姓名： | 戚肖宁 冯之雁 |
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| 作者单位： | 杭州电子工业学院ＩＣＣＡＤ研究所 |
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| 基金项目： | 国家“八·五”重点科技攻关项目 |
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| 摘 要： | 本文提出了时延驱动布图规划的思想。在用改进的广义力矢量法优化功能单元间连线时延的同时，运算非线性规划的方法进一步优化关键路径上功能单元的时延及连线时延。结果表明，这是一种有效的优化版图时延的方法。
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| 关 键 词： | VLSI 集成电路 时延驱动布图 布图规划 |
Timing Driven Floorplanning |
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| Qi Xiaoning,Feng Zhiyan,Yan xiaolang.Timing Driven Floorplanning[J].Acta Electronica Sinica,1995,23(2):103-105. |
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| Authors: | Qi Xiaoning Feng Zhiyan Yan xiaolang |
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| Abstract: | In this paper,we present the idea of timing driven floorplanning.While optimizing the interconnection delay between cells using improved GFDR,We use nonlinear programming method to reduce the cell delays and interconnection delays in critical paths.The result shows that it is an effective method for optimizing layout delay of VLSI. |
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| Keywords: | VLSI Timing driven layout Floorplanning |
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