| 无失真并行数据压缩的脉动阵列ASIC设计 |
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| 引用本文： | 顾静,帅典勋,顾清.无失真并行数据压缩的脉动阵列ASIC设计[J].电子学报,2000,28(9):135-136. |
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| 作者姓名： | 顾静 帅典勋 顾清 |
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| 作者单位： | 1. 华东理工大学计算机科学与工程系,上海 200237;2. 清华大学智能技术和系统国家重点实验室,北京 100084 |
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| 基金项目： | 973国家重点基础研究规划项目基金!(No .G1 9990 32 70 7)，国家自然科学基金!(No .697730 37) |
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| 摘 要： | 本文提出适用于无失真并行数据压缩的超大规模ASIC的逻辑电路设计.与其他传统的串行或小规模并行无失真数据压缩的硬件或软件方法相比,本文的Systolic阵列结构有更好的并行性、实时性和普适性.对ASIC的时序和功能进行的模拟验证,证明了逻辑和电路设计的正确性和有效性.
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| 关 键 词： | 数据压缩 遗传算法 功能模拟 时序模拟 |
| 收稿时间： | 1999-07-15 |
A Systolic ASIC Scheme for Undistorted Parallel Data Compression |
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| GU Qing,SHUAI Dian-xun,GU Jing.A Systolic ASIC Scheme for Undistorted Parallel Data Compression[J].Acta Electronica Sinica,2000,28(9):135-136. |
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| Authors: | GU Qing SHUAI Dian-xun GU Jing |
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| Affiliation: | 1. Department of Computer Science and Engineering,East China University of Science and Technology, Shanghai 200237;2. State Key Laboratory of Intelligence Technology and System,Tsinghua University,Beijing 100084,China |
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| Abstract: | This paper presents a new systolic ASIC scheme to implement the undistorted parallel data compression algorithm based on genetic algorithm (GA).In comparison with other traditional sequential or small scale parallel methods of data compression,the proposed systolic scheme has much higher parallelism,real time performance and more suitability.The simulation of timing performance and functionality for the ASIC scheme verifies its correctness and effectiveness. |
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| Keywords: | data compression genetic algorithm timing simulation functional simulation ASIC (Application Specific Integrated Circuit) |
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