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Formula approximation for flat and hierarchical symbolic analysis
Authors:F V Fernández  A Rodríguez-Vázquez  J D Martín  J L Huertas
Affiliation:(1) Department of Design of Analog Circuits, Centro Nacional de Microelectrónica, Edificio CICA, Avda Reina Mercedes s/n, 41012 Sevilla, Spain
Abstract:This paper addresses the topic of reducing the complexity of formulae resulting from the symbolic analysis of analog integrated circuits, covering both flat and hierarchical symbolic analysis approaches. Previously reported criteria for flat analysis are first briefly reviewed and their limitations illustrated via examples of practical analog circuits. In all of these criteria simplifications are performed by estimating the numerical values of the symbolic terms at a single point of the parameter space, corresponding to the expected typical values for symbols. Consequent quantitative as well as qualitative inaccuracies resulting from this approach are identified. A new simplification strategy for flat symbolic approaches is then presented in which insignificant terms are deleted taking into account expected ranges of variation in the symbol values. Examples are used to show that this new criterion overcomes the drawbacks encountered in previous ones. Finally, an algorithm to simplify hierarchical formulae is presented which includes consideration of the potential ranges of variation in the symbolic parameter values. This algorithm is also applied to practical analog integrated circuits.1. Most of the results in this paper have been obtained with a 4-Mips and 8-Mbyte physical memory SUN3/260 workstation.2. In the rest of the paper the concept offormula complexity denotes the number of symbolic terms contained in a formula. Each addend in (4) is considered as a term to this purpose.3. For instance, simplification of the voltage gain for the folded cascode OTA of figure 1b, with a maximum error margin of 60% (isin M = 0.6), yields a dc gain deviation of 1.6% 9].4. An analog schematic is said to be sized when a numerical value has been assigned to each circuit element and model parameter.5. In practice a sufficiently fine grid should be defined inside that region.6. Here, ldquosymbolrdquo is generally applied, in the sense that it may either denote a parameter space variable, a product of variables, or a sum of products.7. The models used in this example are intended only as an illustration. Hence, they do not include all the issues required for practical transconductance amplifier applications.
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