Analysis of copper grains in damascene trenches after rapid thermal processing or furnace anneals |
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Authors: | Qing-Tang Jiang Matt Nowell Brendan Foran Aaron Frank R H Havemann Vijay Parihar R A Augur J D Luttmer |
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Affiliation: | (1) International Sematech, Austin, TX;(2) Texas Instruments, Dallas, TX;(3) TSL Inc., Draper, UT;(4) Novellus Systems, San Jose, CA;(5) Mattson Technology, Fremont, CA;(6) Philips Semiconductors, Eindhoven, The Netherlands |
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Abstract: | The microstructures of Cu lines in damascene trenches annealed at temperatures from room temperature to 425°C using both rapid
thermal processing (RTP) and furnace annealing were investigated using an array of characterization techniques including transmission
electron microscopy (TEM), focused ion beam, scanning electron microscopy (SEM), and electron backscatter diffraction-orientation-imaging
microscopy (EBSD-OIM). It was found that the final grain sizes strongly depend on the annealing process used; RTP generated
larger grains than furnace annealing. The Cu line electrical resistance correlated with grain size differences observed for
RTP and furnace anneals. The ramping rate, not the annealing time, played the critical role in the grain growth process. In
either case, a high density of Σ3 coincident site lattice (CSL) twin boundaries was observed in the Cu lines. Forty-five percent
of the grain boundaries measured were found to be Σ3 CSL twins, which are differentiated from random high-angle boundaries
by having preferred electrical and diffusion properties. The minimum feature dimension of width or height of the damascene
trenches limited the average grain size. Prior to the trench height limitation, the average grain size increased linearly
with the trench width. The Cu (111) texture became stronger as the trench width increased up to 0.5 μm; for wider trenches,
the texture did not increase further. |
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Keywords: | Damascene Cu line grain size grain growth crystallographic orientation anneal resistance |
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