Efficient Realization of Large Size Two’s Complement Multipliers Using Embedded Blocks in FPGAs

This paper presents an optimized design approach for two’s complement large size multipliers using smaller size embedded multiplier blocks available as resources in field programmable gate arrays (FPGAs). The realization is based on the Baugh–Wooley algorithm, which segments the multiplication into unsigned and signed components. To achieve efficient implementation results, a set of optimized schemes for the realization of the additions required for the unsigned multipliers and for combining the unsigned and signed components is proposed. The implementations of the multipliers have been carried out for operands with sizes ranging from 20 to 128 bits. The designs are synthesized and implemented on Xilinx’s Spartan-3 in the ISE 8.1 design platform and compared with three other realizations using the following approaches: (1) conventional sign-extension approach, (2) Xilinx’s IP-Core generator, and (3) sign-and-magnitude-based approach. The experimental results indicate that our proposed method outperforms the other techniques.