基于FPGA的24点离散傅里叶变换结构设计

基于Good—Thomas映射算法和ISE快速傅里叶变换IP核，设计了一种易于FPGA实现的24点离散傅里叶变换，所设计的24点DFF模块采用流水线结构，主要由3个8点FFT模块和1个3点DFT模块级联而成。并且两级运算之间不需要旋转因子，整个DFF模块仅仅需要14个实数乘法器，布局布线后仿真工作时钟频率可达200MHz。首先根据Good—Thomas算法将并行的24路输入信号分成3组，每组8路信号，并进行并／串转换，得到3路串行信号；其次。将3路串行信号分别输入至3个FFrIP核模块进行8点FFT运算；然后，将上述3个FFrIP核模块同一时刻输出的3路信号进行3点DFF变换；最后，将得到的3路并行输出信号分别进行串／并转换，得到24路DFF输出信号。此外，设计的24点DFT结构还具有很好的扩展性，通过修改FFTIP核变换点数参数便可实现长度N=3×2^N点DFT。

Structural Design and Implementation of FPGA-based 24-point Discrete Fourier Transform

A structure of 24-point Discrete Fourier Transform(DFT) for FPGA implementation is designed based on the Good-Thomas mapping algorithm and the ISE Fast Fourier Transform(FFT) IP core in this paper.The proposed 24-point DFT module employs the pipeline structure and is composed mainly of three 8-point FFT modules and one 3-point DFT module.The proposed 24-point DFT module can stably work at a clock frequency of 200MHz,and it only requires 14 multipliers.Firstly,according to the Good-Thomas mapping algorithm,the 24-channel input signals are divided into three groups,each of which contains 8-channel input signals.Secondly,a parallel-to-serial conversion is performed on each group of signals,respectively.Thirdly,an 8-point FFT is performed on each group of conversed signals via the FFT IP core provided by the ISE10.1 software.Fourthly,the output signals of the above three 8-point FFT modules are simultaneously transferred into a 3-point DFT module.Lastly,each channel of the output signal from the 3-point DFT module is converted into 8-channel signals via a serial-to-parallel conversion,and then the final 24-channel output signals are obtained.In addition,the proposed DFT structure has good extensibility.By simply modifying the corresponding parameters of the employed FFT IP core,the above structure of 24-point DFT can adapt to the DFT implementation with a length of N=3×2n.