| 基于RTL级USB 2.0协议层的设计与实现 |
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| 引用本文： | 车娟,吴士萍,黄君凯.基于RTL级USB 2.0协议层的设计与实现[J].电子工程师,2004,30(1):59-62. |
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| 作者姓名： | 车娟 吴士萍 黄君凯 |
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| 作者单位： | 暨南大学电子系,广东省广州市,510632 |
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| 摘 要： | 在分析了USB2．0协议层通信原理的基础上，采用模块划分方法，将协议层划分为3个主要模块，运用Verilog HDL语言完成了RTL(寄存器传输级)设计，并在Cadence软件Verilog-XL上通过了行为仿真。最后通过Xilinx公司的FPGA Virtex芯片加以实现，以Xilinx ISE软件布线后，仿真结果显示速度达到52MHz，完全满足USB2．0协议的要求。
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| 关 键 词： | RTL USB2.0 通用串行总线 寄存器传输级 协议层 |
| 修稿时间： | 2003年6月18日 |
Design and Realization of USB 2.0's Protocol Layer Based on RTL |
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| Che Juan,Wu Shiping,Huang Junkai.Design and Realization of USB 2.0''''s Protocol Layer Based on RTL[J].Electronic Engineer,2004,30(1):59-62. |
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| Authors: | Che Juan Wu Shiping Huang Junkai |
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| Abstract: | The realization of protocol layer of USB2.0 system based on RTL is presented in this paper .After analyzing the communication theory , protocol layer is partitioned into three main modules, and it is implemented with FPGA Virtex chip of Xilinx company. The result shows that its speed is up to 52 MHz which fully satisfies the request of USB 2.0 specification. |
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| Keywords: | USB USB 2 0 protocol layer state machine RTL |
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