CMOS毫米波低相噪级联双锁相环频率综合器设计

采用65 nm CMOS工艺，设计了一种低相噪级联双锁相环毫米波频率综合器。该频率综合器采用两级锁相环级联的结构，减轻了单级毫米波频率综合器带内和带外相位噪声受带宽的影响。时间数字转换器采用游标卡尺型结构，改善了PVT变化下时间数字转换器的量化线性度。数字环路滤波器采用自动环路增益控制技术来自适应调节环路带宽，以提高频率综合器的性能。振荡器采用噪声循环技术，减小了注入到谐振腔的噪声，进而改善了振荡器的相位噪声。后仿真结果表明，在1.2 V电源电压下，该频率综合器可输出的频率范围为22～26 GHz,在输出频率为24 GHz时，相位噪声为-104.8 dBc/Hz@1 MHz,功耗为46.8 mW。

Design of a CMOS Millimeter-Wave Low-Phase-Noise Cascaded Dual Phase-Locked Loop Frequency Synthesizer

A low-phase-noise cascaded dual phase-locked loop millimeter-wave frequency synthesizer was designed in a 65 nm CMOS technology. A two-stage phase-locked loop cascaded structure was adopted to reduce the influence of bandwidth constraints on the phase noise in band and out of band of the single-stage system in millimeter-wave frequency synthesizer. The vernier structure was adopted in time-to-digital converter to improve the quantization linearity during the time-to-digital convert under PVT changes. The automatic loop gain control technology was used in digital loop filter to adaptively adjust the loop bandwidth to improve the performance of the frequency synthesizer. The noise circulating technology was adopted in oscillator to reduce the injected noise of resonator so as to improve the phase noise of oscillator. The post-simulation results show that the frequency range of the frequency synthesizer is 22-26 GHz under a supply voltage of 1.2 V. When the output frequency is 24 GHz, the phase noise is -104.4 dBc/Hz @1 MHz, and the power consumption is 46.8 mW.