采用基本门单元完全测试矢量的测试生成算法

文章介绍了一种采用基本逻辑门单元的安全测试矢量集生成测试矢量的方法，该方法可以将搜索空间限制在2(n 1）种组合内。它采用故障支配和故障等效的故障传播、回退等技术，建立了一套从局部到全局的测试生成新方法。同时，利用基本门单元安全测试矢量的规律性，可以实现最小的内存容量要求。在一些基准电路的应用实例中，得到了满意的结果。

Test Generation Algorithm Using Complete Test Vector of the Primitive Gates

A novel algorithm for test generation using complete test vector of the primitive gates is proposed, which refines the search space to 2(n+1). The notions of fault dominance and fault equivalence are utilized in the process of propagation and backtrack. These techniques lead to a new test generation algorithm, in which a more global approach to test generation can be obtained by adopting a local view of the overall test generation problem. Moreover, with the natural regularity of the complete test of primitive gates, this new algorithm only needs a minimal capacity of memory. Experiments on some benchmark circuits show that satisfactory results can be obtained.