一种低延迟极化码串行抵消译码器设计

为了克服5G移动通信系统中极化码串行抵消(SC)译码算法延迟高、计算复杂度高、硬件结构复杂度高等问题,基于冻结比特、冻结比特对和冻结区间等方式,提出了冻结比特设计模式。该设计模式包含基于冻结比特对的译码延迟和计算复杂度的分析方法。通过优先剪枝冻结比特结点的方式,进一步化简SC译码树,提高了搜索译码树的速度。码长为1 024的改进流水线树型SC译码器基于FPGA平台实现。实验结果表明,译码延迟为2.35μs,数据吞吐率为435 Mbit/s。与现有译码器相比,该译码器的译码延迟、数据吞吐率分别优化了9.6%、10.4%。

Design of a Low-Latency Polar Code Successive Cancellation Decoder

In order to overcome the problems of high latency, high computational complexity and high hardware structure complexity of successive cancellation(SC) decoding algorithm in 5 G mobile communication systems, the freezing bit design pattern was proposed based on frozen bit, frozen bit pair and frozen interval. The design pattern included the analysis method of decoding latency and calculation complexity. The SC decoding tree was further simplified by preferentially pruning frozen bit nodes, thereby speeding up the search decoding tree. An improved pipelined tree SC decoder with N = 1 024 was implemented based on the FPGA platform. Experimental results showed that the decoding latency was 2.35 μs and the data throughput was 435 Mbit/s. Compared with the existing decoder, the decoding latency and data throughput of the decoder were optimized by 9.6% and 10.4%, respectively.