| 基于JESD204B的射频信号高速采集系统设计 |
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| 引用本文： | 和,爽.基于JESD204B的射频信号高速采集系统设计[J].电子器件,2020,43(1):124-127. |
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| 作者姓名： | 和 爽 |
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| 作者单位： | 中北大学电子测试技术国家重点实验室 |
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| 摘 要： | 为了解决传统转换器传输接口传输速率低、抗干扰差、布局布线面积大等问题,设计了一种基于JESD204B的射频信号高速采集系统。系统对接收到的射频信号进行下变频处理,通过高速ADC对解调基带信号直接采样,采样后的数字基带信号通过自主设计的JESD204B接口逻辑传输至FPGA并缓存。测试结果表明,系统可实现1.0 Gsample/s采样率的直接采样,数据传输速率可达10 Gbit/s,且数据链路稳定可靠。
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| 关 键 词： | 高速采集系统 JESD204B FPGA 正交解调 乒乓操作 |
Design of High-Speed Acquisition System of RF Signal Based on JESD204B |
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| HE Shuang,WANG Hongliang.Design of High-Speed Acquisition System of RF Signal Based on JESD204B[J].Journal of Electron Devices,2020,43(1):124-127. |
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| Authors: | HE Shuang WANG Hongliang |
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| Affiliation: | (National Key Laboratory For Electronic Measurement Technology,Key Laboratory of Instrumentation Science and Dynamic Measurement,Ministry of Education,North University of China,Taiyuan 030051,China) |
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| Abstract: | In order to solve the problems of low transmission rate,poor anti-interference and large layout area of traditional converter transmission interface,a high-speed acquisition system of RF signal based on JESD204B is designed.The received RF signal is down-converted,the demodulated baseband signal is directly sampled by the high-speed ADC.The sampled digital baseband signal is transmitted to the FPGA through the self-designed JESD204B interface and buffered.Test results show that the system can achieve direct sampling with a sampling rate of 1.0 Gsample/s and a data transmission rate of up to 10 Gbit/s,and the data link is stable and reliable. |
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| Keywords: | high speed acquisition JESD204B FPGA quadrature demodulation ping-pong operation |
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