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Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices |
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| Authors: | Fu Zuozhen Yin Huaxiang Ma Xiaolong Chai Shumin Gao Jianfeng Chen Dapeng |
| Affiliation: | Key Laboratory of Microelectronics Devices and Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China |
| Abstract: | |
| Keywords: | metal gate stress 20 nm CMOS devices high-k/metal gate PVD TiNx |
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