| 基于刻蚀工艺的IC关键面积计算模型与实现方法 |
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| 引用本文： | 赵天绪,郝跃,马佩军.基于刻蚀工艺的IC关键面积计算模型与实现方法[J].半导体学报,2002,23(1):102-106. |
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| 作者姓名： | 赵天绪 郝跃 马佩军 |
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| 作者单位： | [1]西安电子科技大学微电子所，西安710071 [2]宝鸡文理学院数学系，宝鸡721007 |
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| 摘 要： | 在 IC的制造过程中 ,由于工艺的随机扰动 ,过刻蚀和欠刻蚀造成了导线条的宽度和线间距的变化 .论文在分析过刻蚀和欠刻蚀对 IC版图影响的基础上 ,提出了基于工艺偏差影响的 IC关键面积计算新模型和实现方法 .模拟实验表明模拟结果与理论分析是一致的
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| 关 键 词： | 关键面积 随机扰动 缺陷 |
Computation Model and Realization Method of IC Critical Area Based on Etching Process |
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| Zhao Tianxu ,Hao Yue and Ma Peijun.Computation Model and Realization Method of IC Critical Area Based on Etching Process[J].Chinese Journal of Semiconductors,2002,23(1):102-106. |
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| Authors: | Zhao Tianxu Hao Yue and Ma Peijun |
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| Affiliation: | Zhao Tianxu 1,2,Hao Yue 1 and Ma Peijun 1 |
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| Abstract: | Over etching or under etching in IC process causes the variation of the linewidth and spacing between two parallel lines because of the random disturbance of the process.The influence on over etching and under etching to IC layout is analyzed,the computation model and realization method of IC critical area are presented.The simulation result is in agreement with the theoretical analysis. |
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| Keywords: | critical area random disturbance defect |
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