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低功耗CMOS逻辑电路设计综述
引用本文:甘学温,莫邦燹.低功耗CMOS逻辑电路设计综述[J].微电子学,2000,30(4):263-267.
作者姓名:甘学温  莫邦燹
作者单位:北京大学,微电子所,北京,100871
摘    要:分析了CMOS逻辑电路的功耗来源从降低电源电压、减 上负载电容和逻辑电路开关活动几率等方面论述了降国耗的途径。讨论了深亚微米器件中亚同值电流对功耗的影响以及减小亚阈值电流的措施,最后分析了高层次设计对降低功耗的关键作用,说明低功耗设计必须从设计的各个层次加在考虑,实现整体优化设计。

关 键 词:VLSI  CMOS逻辑电路  低功耗电路  电路设计
文章编号:1004-3365(2000)04-0262-05
修稿时间:1999-12-21

An Overview of Low-Power Digital CMOS Design
GAN Xue-wen,MO Bang-xian.An Overview of Low-Power Digital CMOS Design[J].Microelectronics,2000,30(4):263-267.
Authors:GAN Xue-wen  MO Bang-xian
Abstract:Sources of power consumption for digital CMOS are analyzed. Approaches to minimizing power consumption of the CMOS logic circuit by scaling supply voltage and decreasing capacitance and transition activities are described' Effects of the subthreshold current on the power consumption in deep submicron devices are discussed, and strategies to restrain subthreshold current are dealt with. Techniques for low-power design are examined in terms of technology,logic style,circuit architecture and algorithm optimizations.
Keywords:VLSI  CMOS digital circuit  Low power circuit  Deep submicron device
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