| Viterbi译码器的FPGA实现技术研究 |
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| 引用本文： | 孙晓岩,付永庆,张文鑫.Viterbi译码器的FPGA实现技术研究[J].应用科技,2003,30(5):11-13. |
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| 作者姓名： | 孙晓岩 付永庆 张文鑫 |
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| 作者单位： | 哈尔滨工程大学,信息与通信工程学院,黑龙江,哈尔滨,150001 |
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| 摘 要： | 提出了一种实现高速并行Viterbi译码器的结构，并且将SMDO法^1]用于幸存路径存储和输出模块部分．本设计已基于FPGA得以实现，获得了译码速度快、延时小的效果．
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| 关 键 词： | Viterbi译码器 FPGA 译码速度 路径度量存储模块 |
| 文章编号： | 1009-671X(2003)05-0011-03 |
| 修稿时间： | 2002年12月2日 |
Technology of implementing Viterbi decoder based on FPGA |
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| SUN Xiao yan,FU Yong qing,ZHANG Wen xin.Technology of implementing Viterbi decoder based on FPGA[J].Applied Science and Technology,2003,30(5):11-13. |
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| Authors: | SUN Xiao yan FU Yong qing ZHANG Wen xin |
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| Abstract: | A new Viterbi decoder with a high rate and parallel structure was presented. A new survivor memory and decoding output (SMDO) method presented was used to implement the new structure. An FPGA based Viterbi decoder was obtained. On the basis of the results of simulations, its advantages in decoding speed and time delay was shown as well. |
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| Keywords: | Viterbi decoder FPGA |
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