抗谐波锁定的延时锁相环

为了解决传统延时锁相环(DLL)结构在宽频率锁定范围中的无法锁定和谐波锁定问题,在传统DLL结构中加入启动控制电路,使DLL在上电阶段把环路滤波电容上的电压充电至电源电压,从而使压控延时线的初始延时在上电后达到最小,并且小于输入参考信号的1个周期.设计了带开关控制的鉴相器,将DLL的锁定过程分为粗调和微调两个阶段,压控延时线的延时在粗调阶段只能逐渐增大,在微调阶段微调,直到延时为输入参考信号的1个周期,从而克服了无法锁定以及谐波锁定的问题,而且减小了DLL的锁定时间.采用GSMC 0.13μm1P7MCMOS工艺设计、1.2 V的电源电压进行仿真,结果表明该DLL工作频率范围为300～500MHz,功耗小于3mW.

Anti-Harmonic Lock Delay-Locked Loop

This paper proposes a Dely-Locked Loop with new structure, A start contrl circuit, which can makes the loop filter be precharged to the power supply voltage during power on, is added into the convetional DLL, hence the intitial delay of voltage controlled delay line is at minimum when the power on is over; The novel phase detector with switch makes the DLL locking process having two stages, one locking stage is coarse tuning stage, the other is fine tuning stage, The coarse tuning stage not only makse the DLL successfully overcoming the harmonic lock and failure lock during wide range operation, but also reduces the locking time, The locking capture range of the switch controlled phase detector is (-2π, +2π), enlarging the range (-π, +π) of the conventional phase detector, therefore, the operating frequency range of the DLL is extened, This DLL is designed and simulated under the power supply of 1.2V in GSMC 0.13- 1p7M CMOS technology, Simulation results show that the operating frequency range is from 300M to 500M, the static locking error is less than 10ps, and the total power is less tahn 3mW.