分像素插值算法的VLSI实现

针对H.264/AVC标准中分像素插值运算复杂度高和存储访问量大的问题, 提出新的分像素插值算法。该算法采用易于硬件实现的4阶滤波器取代6阶滤波器进行分像素插值； 基于算法给出了一种1/4像素精度的8×8 块插补流水线结构。经性能分析和滤波器结构比较表明, 该结构在一个时钟内可以完成32个1/2像素位置的插值运算, 可应用于所有大小块, 且有面积小, 速度快的特点。实验结果表明, 与H.264标准相比, 该算法可以降低15%的空间复杂度, 提高了峰值信噪比, 降低了比特率, 提高了编码性能。

VLSI Implementation for Sub-Pixel Interpolation Algorithm

To resolve the problems of high complexity of sub-pixel interpolation operation and large access volume of storage in H.264/AVC standard, a kind of sub-pixel interpolation operation is presented. It replaces the 6 order filter with a 4 order filter which is easy for hardware implementation of sub-pixel interpolation. Based onthe algorithm, a kind of 1/4 pixel precision interpolative pipeline architecture for 8×8 basic block is proposed. It is indicated by the performance analysis and filter structure that the structure can complete 32 interpolation operationsof 1/2 pixel location in one clock period, which can be applied to data block with a variety of size. It has the characteristics of small area and fast speed. The experimental results show that compared with H.264 standard, the new algorithmis able to reduce space complexity by 15%, improve PSNR(Peak Signal to Noise Ratio), reduce bit rate and improve the performance of coding.