| 基于单片SRAM的EDAC电路设计 |
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| 引用本文： | 解彦,周昌义,周盛雨,石磊.基于单片SRAM的EDAC电路设计[J].微计算机信息,2011(7). |
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| 作者姓名： | 解彦 周昌义 周盛雨 石磊 |
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| 作者单位： | 中国科学院研究生院;中国科学院空间科学与应用研究中心; |
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| 摘 要： | 在航天应用中,为了减少单粒子翻转效应的影响,星载计算机的RAM存储单元采用检错纠错(EDAC)设计。本文介绍了EDAC原理,并对EDAC电路组成进行改进,将数据和校验存储在一片64Kx8的SRAM中,通过FPGA内部逻辑实现EDAC功能和RAM读写控制,增加了纠错回写和纠错计数功能,并提供测试验证EDAC功能的方法。
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| 关 键 词： | FPGA EDAC SRAM SEU |
The Design Of An EDAC Circuit Based On Single SRAM |
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| XIE Yan ZHOU Chang-yi ZHOU Sheng-yu SHI Lei.The Design Of An EDAC Circuit Based On Single SRAM[J].Control & Automation,2011(7). |
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| Authors: | XIE Yan ZHOU Chang-yi ZHOU Sheng-yu SHI Lei |
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| Affiliation: | XIE Yan ZHOU Chang-yi ZHOU Sheng-yu SHI Lei (Graduate University of Chinese Academy of Sciences,100190,Beijing,China) (Center for Space Science and Applied Research Chinese Academy of Sciences,China) |
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| Abstract: | To mitigate the effect of single event upset (SEU), EDAC technology is often applied on on-board computer RAM. This paper presents the principle of EDAC, and improves the EDAC circuit by the use of single SRAM for data and parity storage, thus saving PCB areas, reducing costs. Finally a method of verifying the EDAC function is proposed. |
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| Keywords: | FPGA EDAC SRAM SEU (Single Event Upset) |
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