Design of CMOS Ternary Latches |
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Authors: | Shou X Kalantari N Green M M |
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Affiliation: | Linear Technol. Corp, North Chelmsford, MA; |
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Abstract: | This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-mum CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches |
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