基于标准单元库扩展的快速乘法器设计

设计并实现17×17 bit带符号数字乘法器。为了提高乘法器的性能,采用改进的Booth编码算法、Wal-lace树型结构以及基于标准单元库扩展的设计方法。该方法使用逻辑功效模型分析乘法器的关键路径,通过构造驱动能力更为完备的单元以实现关键路径中每一级门功效相等,从而得到最短路径延时。将TSMC 90 nm标准单元库扩展得到扩展单元库,使用两个单元库版图分别实现数字乘法器,基于扩展单元库实现的乘法器速度提升10.87%。实验结果表明,基于标准单元库扩展的半定制设计方法可以有效提升电路的性能,这种方法尤其适用于电路负载过大的情况。

Design of high-speed multiplier based on standard cell library extension

This paper proposed a 17×17 bit signed digital multiplier. To improve the performance, the multiplier used modified Booth's recoding algorithm, a Wallace tree structure and design method based on standard cell library extension. It analyzed critical path using logical effort model, and by constructing cells with different driving capabilities, it implemented equal logical effort in each stage to achieve minimum path delay. Based on TSMC 90 nm standard cell library, generated an extended cell library, and implemented the layouts of multiplier respectively. Compared to standard cell library, the multiplier implemented with extended cell library achieved a performance improvement of 10.87%. Experimental results show that the semi-custom design methodology based on standard cell library extension can improve circuit performance effectively, which is especially appropriate for designs with large loads.