基于FPGA的SDRAM控制器设计与实现

针对SDRAM(Synchronous Dynamic Random Access Memory)在缓存图像数据时时序的控制比较复杂的问题,在研究SDRAM的特点和原理的基础上,提出了一种基于现场可编程逻辑器件FPGA(Field Programmable Gate Array)为核心的SDRAM控制器的设计方案。采用分模块的思想,把SDRAM的控制分成不同的功能模块,各模块之间通过信号状态线相互关联,并且相关模块利用状态机来控制整个时序的过程。另外,为了提高SDRAM的缓存速度,选择了SDRAM工作在页突发操作模式下,使SDRAM的读写速度有了大幅的提升。整个控制系统经过仿真和在线逻辑分析仪验证表明:控制器能准确地对SDRAM进行读写控制,稳定可靠,可应用于不同的高速缓存系统。

Design and Implementation of SDRAM Controller Based on FPGA

According to the problem controling the SDRAM(Synchronous Dynamic Random Access Memory) timing in the cache the image data are complicated, presents a SDRAM controller design based on a core of FPGA(Field Programmable Gate Array). Use the thought divided module,which put the SDRAM controller divide into different functional blocks are connected through the signal state of line, and the associated modules control the whole process through state machine. In addition, in order to improve the speed of the SDRAM buffer, select work mode under the SDRAM page burst.As a result, the speed of SDRAM read and write improved dramatically. The whole control system through simulation and online logic analyzer demonstrate that: SDRAM controller can read and write control accurately, stable and reliable, and it can be applied to different speeding cache systems.