| Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform |
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| 作者姓名： | 陈颖琪 Lin Guixu Wang Feng Hu Jianling Tan Zhiming |
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| 作者单位： | Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R. China |
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| 基金项目： | 国家高技术研究发展计划(863计划) |
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| 摘 要： | A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television （HDTV） system-on-a-chip （SoC） platform, especially when it is a multiple processor system. Based on a general introduction to the whole HDTV SoC platform, a layered interrupt controller and its implementation are discussed in detail. The proposed scheme was implemented in our FPGA verification board. The results indicate that our scheme is reliable and efficient. Meanwhile, as a functional intellectual property （IP）, the interrupt controller has reusability and expandability with the layered structure.
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| 关 键 词： | 高清晰电视 系统芯片 中断控制器 MIPS处理器 |
| 修稿时间： | 2006-04-25 |
Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform |
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| Chen Yingqi,Lin Guixu,Wang Feng,Hu Jianling,Tan Zhiming.Multiple MIPS 4Kc cores based interrupt controller design and its implementation on HDTV SoC platform[J].High Technology Letters,2007,13(3):297-301. |
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| Authors: | Chen Yingqi Lin Guixu Wang Feng Hu Jianling Tan Zhiming |
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| Affiliation: | Shanghai Key Laboratory of Digital Media Processing and Transmission, Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P.R.China |
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| Abstract: | A multiple MIPS 4Kc processor cores based interrupt processing system is introduced. The interrupt controller plays a key role in the high definition television (HDTV) system-on-a-chip (SoC) platform,especially when it is a multiple processor system. Based on a general introduction to the whole HDTV SoC platform, a layered interrupt controller and its implementation are discussed in detail. The proposed scheme was implemented in our FPGA verification board. The results indicate that our scheme is reliable and efficient. Meanwhile, as a functional intellectual property (IP), the interrupt controller has reusability and expandability with the layered structure. |
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| Keywords: | HDTV SoC interrupt controller MIPS processor core |
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