一种改进的反码加法器设计

传统的加法器在有符号数相加时需将操作数转化为补码形式进行运算，运算结束将计算结果再转化为原码。为减少关键路径延迟，在标志前缀加法器的基础上，提出一种改进的反码加法器，将常用反码加法器中的加一单元合并到加法运算中。在SMIC 0.18 μm工艺下，将改进的64位反码加法器与常用的64位补码加法器进行比较，数据显示面积减少了39.1%，功耗降低了39.9%，关键路径延迟降低了5.1%。结果表明，改进的反码加法器性能较优。

Design of Improved One's Complement Adder

Conventional adder adding the required number of signed operands into the form of complement operations，and return a result in signed magnitude number. This paper proposes a new structure one’s complement Signed Adder(SA) based on the flagged prefix adder, which could combine the increment unit with the adder, to reduce the delay of the signed adder. A 64-bits enhanced SA has been implemented in SMIC 180nm CMOS technology. Compared with previous work, the area, power, and delay of our design are decreased by 39.1%, 39.9%, and 5.1%, respectively. Results show that this structure is superior to two’s complement adder.