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A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors
Authors:Kyoung Hwan Yeo Chang Woo Oh Sung Min Kim Min Sang Kim Chang Sub Lee Sung Young Lee Sang Yeon Han Eun Jung Yoon Hye Jin Cho Doo Youl Lee Byung Moon Yoon Hwa Sung Rhee Byung Chan Lee Jeong Dong Choe Ilsub Chung Donggun Park Kinam Kim
Affiliation:R&D Center, Samsung Electron. Co., Kyungki, South Korea;
Abstract:Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.
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