一种新颖的高可靠CMOS SRAM 单元

本文提出了一种新颖的8管抗SUE，高噪声容限的SRAM单元。通过在每个访问晶体管上增加了一个并联的晶体管，上拉PMOS的驱动能力可以设计的比传统单元的PMOS的驱动能力更强，读访问晶体管可以设计得比传统单元的读访问晶体管更弱。因此保持，读噪声容限和临界电荷都有较大提高。仿真结果表明，与传统的6管单元相比，合理设计上拉晶体管尺寸后，临界电荷提高了将近3倍。保持和读静态噪声容限分别提高了72%和141.7%。但该新式单元的面积额外开销为54%，读性能也有所下降，适用于高可靠性应用，如航天，军事等。

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military.