一种支持PMVFAST运动估计算法的VLSI体系结构

在分析PMVFAST算法的基础上，提出了一种支持该算法的灵活、高效和低功耗的体系结构．该体系结构的核心是一个运动估计引擎，它包含3种支持特定范围内任意延时的可变延时单元，使其支持多种搜索模式，并通过重用计算单元实现了基本的独立SAD计算引擎．另外，通过关闭不用的单元和资源复用，该引擎能够有效地降低功耗．分析结果表明，该体系结构比经典的16PE阵列低功耗全搜索体系结构提高约15倍的性能，可以获得接近全搜索的视频质量．

A VLSI Architecture for PMVFAST Block-Based Motion Estimation Algorithm

A flexible, efficient and low power architecture for PMVFAST, an enhancing block-based motion estimation algorithm, is proposed in this paper. The core of the architecture is a motion estimation engine, which supports independent calculation of SAD and several searching patterns with different sizes and types. The engine includes three types of delay variable units, which support arbitrary delay in particular ranges and enable different pattern searching. The engine reuses processing elements to construct a SAD engine and enables basic support of all BMAs. Besides, the engine can reduce power consumption by gating the unused elements and reusing resources. Experimental results verify the superiority of the proposed architecture. Its computing efficiency is about 15 times higher than the well-known low power FS architecture including 16 PEs and its PSNR is similiar to the FS algorithm.