| 一种用于JPEG2000的小波变换VLSI结构设计方法 |
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| 引用本文： | 陈磊,王峰,段淋,周赟.一种用于JPEG2000的小波变换VLSI结构设计方法[J].中国图象图形学报,2007,12(10):1730-1734. |
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| 作者姓名： | 陈磊 王峰 段淋 周赟 |
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| 作者单位： | 上海交通大学电子工程系图像通信与信息处理研究所，上海交通大学上海市数字媒体处理与传输重点实验室 上海200240，上海200240 |
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| 摘 要： | 为了快速地进行小波变换,提出了一种应用于JPEG2000的基于提升格式5/3,9/7统一的离散小波滤波单元;同时对于行列并行滤波,提出了一种控制机制,其在缓存5行的条件下,可完成高速行列并行滤波操作。该方法在保证精度条件下,可以取得较高的硬件利用率,且中间数据暂存空间需求低。然后在提升结构基础上,完成了硬件模块设计,并进行了仿真和FPGA实现。最后用Verilog HDL对系统进行了硬件描述,并在Altera DE2的验证板上的cyclone2 EP2C35FC672芯片上,在Quartus 6.0环境下实现了该结构功能。
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| 关 键 词： | 离散小波变换 统一滤波单元 并行结构 行缓存 |
| 文章编号： | 1006-8961（2007）10-1730-05 |
| 修稿时间： | 2007-05-18 |
A VLSI Architecture Design of 9/7 and 5/3 DWT Filter for JPEG2000 |
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| CHEN Lei,WANG Feng,DUAN Lin,ZHOU Yun,CHEN Lei,WANG Feng,DUAN Lin,ZHOU Yun,CHEN Lei,WANG Feng,DUAN Lin,ZHOU Yun and CHEN Lei,WANG Feng,DUAN Lin,ZHOU Yun.A VLSI Architecture Design of 9/7 and 5/3 DWT Filter for JPEG2000[J].Journal of Image and Graphics,2007,12(10):1730-1734. |
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| Authors: | CHEN Lei WANG Feng DUAN Lin ZHOU Yun CHEN Lei WANG Feng DUAN Lin ZHOU Yun CHEN Lei WANG Feng DUAN Lin ZHOU Yun and CHEN Lei WANG Feng DUAN Lin ZHOU Yun |
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| Affiliation: | Institute of Image Communication and Information Processing, Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240;Shanghai Key Laboratory of Digital Media Processing and Transmissions, Shanghai Jiaotong University, Shanghai |
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| Abstract: | A uniform 9/7 and 5/3 DWT filter by lifting scheme is proposed for JPEG2000.This paper also proposes a control method of row and column parallel filtering with minimum five lines cache.This architecture can achieve higher hardware utilization and lower temporary data storage without losing precision.By using this architecture,we have accomplished the hardware design.The algorithm is described by Verilog HDL,and simulated by modelsim.It is implemented by cyclone2-EP2C35FC672 under Altera DE2 board with Quartus 6.0. |
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| Keywords: | JPEG2000 |
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