ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing

In this paper, a fast yet accurate CMOS analog circuit sizing method, referred to as Iterative Sequential Geometric Programming (ISGP), has been proposed. In this methodology, a correction factor has been introduced for each parameter of the geometric programming (GP) compatible device and performance model. These correction factors are updated using a SPICE simulation after every iteration of a sequential geometric programming (SGP) optimization. The proposed methodology takes advantage of SGP based optimization, namely, fast convergence and effectively optimum design and at the same time it uses SPICE simulation to fine tune the design point by rectifying inaccuracy that may exists in the GP compatible device and performance models. In addition, the ISGP considers the requirement of common centroid layout and yield aware design centering for robust final design point specifying the number of fingers and finger widths for each transistor which makes the design point ready for layout.