| 基于FPGA的EoS系统中帧处理的改进与实现 |
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| 引用本文： | 彭煜,黄红斌,刘伟平,陈舜儿.基于FPGA的EoS系统中帧处理的改进与实现[J].光通信技术,2012,36(3):10-13. |
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| 作者姓名： | 彭煜 黄红斌 刘伟平 陈舜儿 |
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| 作者单位： | 暨南大学电子工程系,广州510632;暨南大学光电信息与传感技术广东普通高校重点实验室,广州510632 |
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| 基金项目： | 广东省教育部产学研结合项目，国家973计划项目 |
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| 摘 要： | 根据ITU-TX.86协议的规定,设计了一种EoS系统,实现了IP数据包在基于SDH的骨干光传输网络中的高速传输。针对现有帧处理方案在帧同步时延和时钟抖动方面存在的问题,提出了改进的快速帧同步机制和时钟提取方案。采用廉价的FPGA硬件编程实现,通过电路综合与时序仿真表明,方案在缩短帧同步时延和消除时钟抖动方面具有较好的效果。
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| 关 键 词： | EoS 快速帧同步 时钟同步 FPGA |
Improvements and implementation of frame processing in EoS system based on FPGA |
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| PENG Yu
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HUANG Hong-bin
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LIU Wei-ping
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CHEN Shun-er.Improvements and implementation of frame processing in EoS system based on FPGA[J].Optical Communication Technology,2012,36(3):10-13. |
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| Authors: | PENG Yu HUANG Hong-bin LIU Wei-ping CHEN Shun-er |
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| Affiliation: | 1,2(1.Department of Electronic and Engineering,Jinan University,Guangzhou 510632, China;2.Key Laboratory of Optoelectronic Information and Sensing Technologies of Guangdong Higher Educational Institutes,Jinan University,Guangzhou 510632,China) |
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| Abstract: | According to the provisions of the ITU-T X.86 agreement,a EoS system has been designed and achieved the high-speed transmission of IP packet in the SDH-based backbone optical transmission network.Frame synchronization delay and clock jitter are existing in the current frame processing program,for the problems,a improved rapid frame synchronization mechanism and clock extraction scheme have been presented.With cheap FPGA hardware programming,circuits integrated and timing simulation shows that the program in terms of shortening the frame synchronization delay and eliminating clock jitter has better results. |
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| Keywords: | EoS fast frame synchronization clock synchronization FPGA |
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