| 基于CMMB标准的新型FFT处理器设计 |
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| 引用本文： | 廖敏超,杨波,陈昕.基于CMMB标准的新型FFT处理器设计[J].电视技术,2009,33(Z1). |
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| 作者姓名： | 廖敏超 杨波 陈昕 |
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| 作者单位： | 北京邮电大学,通信与信息工程学院,北京,100876 |
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| 摘 要： | 针对中国移动多媒体广播(CMMB)系统中高速FFT处理器的设计要求,提出了一种新的适用大点数FFT算法的流水线实现结构.采用了混合基4/2、按频率抽取FFT算法,完成了4 096/2 048点,13 bit位宽,定点复数FFr的设计,两个点数的FFT变换能够采用同一套结构实现,节约了资源.设计全部采用VerilogHDL语言描述并通过FPGA仿真验证.
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| 关 键 词： | 基4蝶形运算单元 流水线 |
Design of Novel FFT Processor Based on CMMB Standard |
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| LIAO Min-chao,YANG Bo,CHEN Xin.Design of Novel FFT Processor Based on CMMB Standard[J].Tv Engineering,2009,33(Z1). |
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| Authors: | LIAO Min-chao YANG Bo CHEN Xin |
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| Affiliation: | LIAO Min-chao,YANG Bo,CHEN Xin(School of Information and Communication Engineering,Beijing University of Posts and Telecommunications,Beijing 100876,China) |
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| Abstract: | A novel 4 096/2 048 points FFT pipeline architecture is presented suitable for China Mobile Multimedia Broadcasting(CMMB) system.In this article,the processor is designed for 4 096/2 048 samples with 13 bit bit-width and fixed point by using mixed radix-4/2 decimation in frequency FFT algorithm.Besides,to reduce hardware consume,the processor can either implement 2 048 or 4 096 points FFT by controlling the data-flow between stages.The whole design is described in VerilogHDL and simulated on FPGA. |
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| Keywords: | FFT |
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