一种SEU硬核检测电路的设计与实现

现有的现场可编程门阵列(FPGA)芯片在进行单粒子翻转(SEU)检错时，只能针对FPGA配置单元进行周期性重复擦写而不能连续检错纠错。为此，设计一种能连续检测SEU错误并实时输出检错信息的硬核检测电路。该设计改进传统FPGA芯片的数据帧存储结构，能对芯片进行连续回读循环冗余校验(CRC)。在FDP3P7芯片上的流片实现结果表明，该电路能在50 MHz工作频率下连续对芯片进行回读CRC校验，并正确输出SEU帧检错信息。

Design and Implementation of SEU Hard Core Detection Circuit

Current Field Programmable Gate Array（FPGA） chip can only be erased and configured periodically and repeatedly during the Single Event Upset（SEU） error detection,and this is not a continuous error detection and correction method.Aiming at this problem,this paper presents a continuous SEU hard core detection circuit with real-time error detection information output for external circuits.The circuit improves the traditional FPGA frame storage structureca and can work continuously for read-back Cyclic Redundancy Check（CRC） without affecting the normal state of FPGA.The design has been used in FDP3P7 FPGA chip which is designed independently.Test results indicate that the SEU hard core detection circuit can work continuously on the configuration bit-stream read-back CRC in the 50 MHz frequency and real-time error detection information output correctly.