A 1-V, 100-MHz, 10-mW cache using a separated bit-line memoryhierarchy architecture and domino tag comparators |
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Authors: | Mizuno H Matsuzaki N Osada K Shinbo T Ohki N Ishida H Ishibashi K Kure T |
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Affiliation: | Central Res. Lab., Hitachi Ltd., Tokyo; |
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Abstract: | A 1-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-μm CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V. This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons |
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