通用异步串行通信接口的IP核设计

面对基于传统IC芯片的微电子应用系统设计技术向基于知识产权核的片上系统SoC技术发展的趋势,以IP构件为基础的设计复用思想已经应运而生。通用异步串行通信接口因其可编程特性和高度兼容性,在各类MCU、MPU以及DSP芯片设计中得到了广泛的应用。本文介绍了一种以状态机为控制核心,内部带有16字节缓冲FIFO的通用异步串行通信接口IP核的设计。本设计采用VHDL语言描述,用FPGA实现并通过了仿真验证。

The Design of the UART IP Core

With the microelectronic system design technology based on traditional IC moving to the System-on-a-Chip (SoC) methodology based on IP, the reuse of IP components emerges. For its advantages of programmability and high compatibility, Universal Asynchronous Receiver/Transmitter (UART) is extensively applied to the design of many kinds of chips, such as MCUs, MPUs and DSPs. This paper presents the design of the UART IP core which is based on the Finite State Machine (FSM) with internal 16-byte FIFOs. The design is originally written in VHDL and then implemented in Field Programmable Gate Array (FPGA) with successful simulation results.