用于CMOS电路平均功耗快速模拟的输入向量对序列压缩方法：理论与实践

过大的平均功耗使芯片产生较多的热量，降低芯片的可靠性及性能，严重时会损坏芯片，因此有效地对电路平均功耗做出精确的估计非常重要。由于实际电路存在时间延迟，而考虑延时的电路功耗模型计算量较大，用模拟方法求取电路平均功耗非常耗时。为了在较短的时间内对VLSI电路的平均功耗做出较为可信的估计，该文提出了一套电路功耗分析理论，并由此给出了一种用于CMOS电路平均功耗快速模拟的输入向量对序列压缩方法，ISCAS85及ISCAS89电路集的实验结果表明这种估计方法具有平均功耗估计值准确和加速明显的优点。

Sequence Compaction for Fast Simulating Average Power Dissipation of CMOS Circuits:Theory and Practice

High average power makes VLSI circuits suffer from great instantaneous current and severe electro-migration, which may lower chip's reliability and performance, even invalidate chip's function. Thus it is very imperative to effectively estimate accurate average power dissipation of circuits. Because it has to take long time to compute power dissipation of CMOS circuits with delay, it needs extensive CPU time for a large input vector pair sequence to simulate the mean power consumption of circuits. At the same time, the power of ideal circuits without delay can be computed with high speed, but can not be used to replace of power of circuits with delay because of intolerable magnitude of error. First, this paper utilizes the statistics to analyze the average power of circuits with delay that consists of delay-free transitions and hazards, and defines that the average power of circuits with delay is composed of instructive transition density produced by delay-free transitions, and different grades transition densities caused by hazards. Then, this paper proves the monotonic increase relation between the average power of CMOS circuits with or without delay that does exist. Last, this paper proposes an approach of sequence compaction for fast simulating average power consumption of CMOS circuits that can get an efficient estimation of the mean dissipation of CMOS circuits in a tolerable period. Experiments with ISCAS85&89 benchmarks demonstrate that this approach saves much more CPU time and can obtain an accurate estimation of mean power.