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| 基于分布式算法的串/并混合构架FIR滤波器设计 | |
| 引用本文： | 朱莉,温坚,卢鑫,覃亚丽.基于分布式算法的串/并混合构架FIR滤波器设计[J].实验室研究与探索,2012,31(6):25-27,31. |
| 作者姓名： | 朱莉 温坚 卢鑫 覃亚丽 |
| 作者单位： | 1. 衢州学院电信学院,浙江衢州,324000 2. 巨化集团公司,浙江衢州,324000 3. 中国兵器装备集团,北京,100089 4. 浙江工业大学信息工程学院,浙江杭州,310032 |
| 摘 要： | 研究基于分布式算法的并行度为2的串/并混合构架FIR数字滤波器设计,提出了一种新的FPGA实现结构。该结构引入一个新的移位累加模块,用于实现2查询表输出的累加运算,采用移位寄存器构建相关控制电路。设计输入精度为8位的FIR滤波器,通过Quartus II 7.1及Modelsim 6.0SE的综合与仿真,以及在EPF10K70RC240-4FPGA目标器件上的实现。结果表明:该结构有效缩减关键路径且简化模块化设计流程,性能获得显著提升。 |
| 关 键 词： | 分布式算法 串/并混合结构 FIR滤波器 FPGA 移位累加 |
Design of a Combined Serial/Parallel FIR Digital Filter Based on Distributed Arithmetic |
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| ZHU Li , WEN Jian , LU Xin , QIN Ya-li.Design of a Combined Serial/Parallel FIR Digital Filter Based on Distributed Arithmetic[J].Laboratory Research and Exploration,2012,31(6):25-27,31. | |
| Authors: | ZHU Li WEN Jian LU Xin QIN Ya-li |
| Affiliation: | 1.College of Electronic and Information Engineering,Quzhou University,Quzhou 324000; 2.Juhua Group Corporation,Quzhou 324000;3.China Southern Industry Group,Beijing 100089; 4.College of Information Engineering,Zhejiang University of Technology,Hangzhou 310032,China) |
| Abstract: | This paper focuses on the design of the combined serial/parallel distributed arithmetic-based FIR digital filter with parallelism N=2,for which a novel architecture of FPGA implementation is proposed.A new module of shift-accumulate is designed to accumulate the outputs of two look-up tables,and the corresponding control circuit is configured by shift-register.A series of FIR filters with an input precision of eight is designed.These proposed filters have been simulated and synthesized with Quartus II 7.1 and implemented with an EPF10K70RC240-4 FPGA device.The result shows that the structure can efficiently reduce the process of critical path and modular design,and the performance can be improved. |
| Keywords: | distributed arithmetic combined serial/parallel architecture FIR filter FPGA shift-accumulate |
| 本文献已被 CNKI 万方数据 等数据库收录！ | |
