用发光显微镜测试控制先进CMOS工艺的多晶硅刻蚀时间

通过结合发光显微镜(EMMI)测试和poly-edge电容测试结构很好地控制了多晶硅刻蚀时间,避免了栅极氧化膜的早期失效.从栅极氧化膜击穿电压的测试结果可以看出,当刻蚀时间较短时,一个晶圆内几乎所有测试结构都呈现早期失效模式.通过延长刻蚀时间,早期失效数逐渐减少,最后可以完全消除早期失效,所有测试结构都为本征失效.为了分析多晶硅刻蚀时间和氧化膜失效模式的关系,对早期失效和本征失效样品进行了发光显微镜测试.Poly-edge电容结构的测试结果表明,过短的刻蚀时间导致了多晶硅在STI沟槽中的残留,硅化工艺后,这些多晶硅会使栅极和衬底短路,从而导致了栅极氧化膜的早期失效.通过延长刻蚀时间,可以有效地清除多晶硅的残留,从而保证栅极氧化膜的可靠性.

Polysilicon Over-Etching Time Control of Advanced CMOS Processing with Emission Microscopy

The emission microscopy (EMMI) test is proposed as an effective method to control the polysilicon over-etching time of advanced CMOS processing combined with a novel test structure,named a poly-edge structure. From the values of the breakdown voltage (Vbd) of MOS capacitors (poly-edge structure) ,it was observed that,with for the initial polysilicon etching-time, almost all capacitors in one wafer failed under the initial failure model. With the increase of polysilicon overetching time, the number of the initial failure capacitors decreased. Finally, no initial failure capacitors were observed after the polysilicon over-etching time was increased by 30s. The breakdown samples with the initial failure model and intrinsic failure model underwent EMMI tests. The EMMI test results show that the initial failure of capacitors with poly-edge structures was due to the bridging effect between the silicon substrate and the polysilicon gate caused by the residual polysilicon in the ditch between the shallow-trench isolation region and the active area, which will short the polysilicon gate with silicon substrate after the silicide process.