| 高速信号采集存储及传输系统的设计与实现 |
| |
| 引用本文： | 杨振家,刘颖杰,邓芳芳,谢华,李力.高速信号采集存储及传输系统的设计与实现[J].电子技术应用,2012,38(9):8-10,17. |
| |
| 作者姓名： | 杨振家 刘颖杰 邓芳芳 谢华 李力 |
| |
| 作者单位： | 电子科技大学自动化工程学院,四川 成都,611731 |
| |
| 摘 要： | 为解决高速数据采集系统中的数据缓存和传输速度瓶颈,设计并实现了一种基于光纤通道协议和DDR2 SODIMM存储的高速数据传输、存储系统。利用Stratix Ⅳ GX系列FPGA和QuartusⅡ中自带的DDR2 IP核以及高速收发器IP核,实现了PCI9056的本地接口、DDR2控制器、光纤通道协议和高速串行数据的转换发送,最终实现了数据的高速存储和传输。
|
| 关 键 词： | 高速信号采集 光纤通道 高速传输 FPGA CPCI DDR2 SDRAM |
Design and implementation of high-speed signal acquisition storage and transmission system |
| |
| Yang Zhenjia
,
Liu Yingjie
,
Deng Fangfang
,
Xie Hua
,
Li Li.Design and implementation of high-speed signal acquisition storage and transmission system[J].Application of Electronic Technique,2012,38(9):8-10,17. |
| |
| Authors: | Yang Zhenjia Liu Yingjie Deng Fangfang Xie Hua Li Li |
| |
| Affiliation: | (School of Automation Engineering,University of Electronic Science and Technology of China,Chengdu 611731,China) |
| |
| Abstract: | To tackle the bottleneck of data-caching and the transmission speed in the high-speed data acquisition system,a new high-speed data transmit-save system is designed in this paper.Via utilizing the Stratix IV GX series FPGA,as well as the built-in DDR2 IP core and high-speed send-receive IP core of Quarturs II,the local port of PCI9056,DDR2 controller,fiber channel protocol and transformation and sending of high-speed serial data are realized.Based on it,a new high-speed data-caching and transmission system is implemented. |
| |
| Keywords: | high speed signal acquisition fiber channel high-speed transmission FPGA CPCI DDR2 SDRAM |
| 本文献已被 CNKI 万方数据 等数据库收录！ |
|
