| 高压缩V-LRU算法的研究与实现 |
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| 引用本文： | 董磊,岑俊龙,涂志娣,李可,梁松海.高压缩V-LRU算法的研究与实现[J].微电子学,2011,41(5). |
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| 作者姓名： | 董磊 岑俊龙 涂志娣 李可 梁松海 |
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| 作者单位： | 1. 深圳大学光电子学研究所,广东深圳,518060
2. 深圳大学信息工程学院EDA技术中心,广东深圳,518060 |
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| 摘 要： | 提出并实现了基于四路组相联高速缓存的高压缩V-LRU算法。该算法将有效位和近似LRU标志位压缩到只有4位,可以大大减少电路面积,且高速缓存的缺失率基本保持不变。在高速缓存容量为8kByte时,高压缩V-LRU算法的缺失率与7-bit位比较近似V-LRU算法、5-bit位复用近似V-LRU算法基本相同,而相对于9-bit近似V-LRU算法也只增加大约0.9%。基于SMIC 0.13μm工艺,高压缩V-LRU算法的电路面积相对于9-bit、7-bit和5-bit V-LRU算法,分别减少10 925.8μm2、6 415.5μm2和2 142.1μm2。而且,如果增加高速缓存的容量,4种近似V-LRU算法缺失率的差别将变得更小,但是,高压缩V-LRU算法的电路面积优势将会更加明显。
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| 关 键 词： | 高压缩V-LRU算法 近似LRU算法 4路组相联 高速缓存 缺失率 |
Study on Highly Compressed V-LRU Algorithm and Its Implementation |
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| DONG Lei,CEN Junlong,TU Zhidi,LI Ke,LIANG Songhai.Study on Highly Compressed V-LRU Algorithm and Its Implementation[J].Microelectronics,2011,41(5). |
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| Authors: | DONG Lei CEN Junlong TU Zhidi LI Ke LIANG Songhai |
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| Affiliation: | DONG Lei1,CEN Junlong2,TU Zhidi1,LI Ke2,LIANG Songhai2(1.Institute of Optoelectronics,Shenzhen University,Shenzhen,Guangdong 518060,P.R.China,2.The EDA Technology Center,College of Information Engineering,P.R.China) |
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| Abstract: | A highly-compressed V-LRU algorithm was proposed and implemented based on 4-way set-associative cache,which compressed the valid flag and pseudo-LRU flags to only four bits.With this algorithm,hardware area could be greatly reduced,while miss rate of the cache remain unchanged.For an 8 kByte cache,miss rate of the highly compressed V-LRU algorithm was similar to 7-bit bit-compared pseudo V-LRU algorithm and 5-bit bit-reused pseudo V-LRU algorithm;and compared to 9-bit pseudo V-LRU algorithm,it increased by ... |
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| Keywords: | Highly-compressed V-LRU algorithm Pseudo LRU algorithm 4-way set-associative Cache Miss rate |
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