High-speed CMOS demultiplexer with redundant multi-valued logic |
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Authors: | J B Kim S H Ahn |
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Affiliation: | 1. Department of Electronics Engineering , Kangwon National University , Republic of Korea kimjb@kangwon.ac.kr;3. R&4. D Division, Dongbu HiTeK Co. Ltd , Republic of Korea |
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Abstract: | This paper describes an 11-Gb/s CMOS demultiplexer with redundant multi-valued logic. The proposed circuit receives serial binary data which is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the redundant multi-valued logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. The circuit is designed with a 0.35?µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The demultiplexer is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43?mW. This circuit is expected to operate at a higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency. |
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Keywords: | Redundant multi-valued logic Multi-valued logic Demultiplexer High-speed interface circuit |
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