65 nm互补金属氧化物半导体场效应和晶体管总剂量效应及损伤机制

对65 nm互补金属氧化物半导体工艺下不同尺寸的N型和P型金属氧化物半导体场效应晶体管(NMOSFET和PMOSFET)开展了不同偏置条件下电离总剂量辐照实验.结果表明:PMOSFET的电离辐射响应与器件结构和偏置条件均有很强的依赖性,而NMOSFET表现出较强的抗总剂量性能;在累积相同总剂量时,PMOSFET的辐照损伤远大于NMOSFET.结合理论分析和数值模拟给出了PMOSFET的辐射敏感位置及辐射损伤的物理机制.

Radiation effect and degradation mechanism in 65 nm CMOS transistor

Radiation effect of deep submicron semiconductor device has been extensively studied in recent years. However, fewer researches laid emphasis on the degradation characterization induced by total ionizing dose (TID) damage in nano-device. The purpose of this paper is to analyze the TID effect on the 65 nm commercial complementary metal oxide semiconductor transistor. The n-type and p-type metal oxide semiconductor field effect transistors (NMOSFET and PMOSFET) with different sizes are irradiated by ⁶⁰Co γ rays at 50 rad (Si)/s, and TID is about 1 Mrad (Si). Static drain-current I_D versus gate-voltage V_G electrical characteristics are measured with semiconductor parameter measurement equipment. The irradiation bias of NMOSFET is as follows:the ON state is under gate voltage V_G=+1.32 V, drain voltage V_D is equal to source voltage V_S (V_D=V_S=0), and the OFF state is under drain voltage V_D=+1.32 V, gate voltage V_G is equal to source voltage V_S (V_G=V_S=0). The irradiation bias of PMOSFET is follows:the ON state is under gate voltage V_G=0 V, drain voltage V_D is equal to source voltage V_S (V_D=V_S=1.32 V), and the OFF state is under V_D=V_G=V_S=+1.32 V. The experimental results show that the negative shifts in the threshold voltage are observed in PMOSFET after irradiation. Besides, for PMOSFET the degradation of the ON state during radiation is more severe than that of the OFF state, whereas comparatively small effect are present in NMOSFET. Through experimental data and theoretical analysis, we find that the changes in the characteristics of the irradiated devices are attributed to the building up of positive oxide charges in the light doped drain (LDD) spacer oxide, rather than shallow trench isolation oxide degradation. The positive charges induced by TID in PMOSFET LDD spacer oxide will lead to the change of hole concentration in channel, which causes the threshold voltage to shift. What is more, the difference in electric field in the LDD spacer is the main reason for the difference in the radiation response between the two radiation bias conditions. Radiation-enabled technology computer aided design used to establish two-dimensional mode of the transistor. The simulation results of I_D-V_G curves are in good agreement with the experimental results. Combining theoretical analysis and numerical simulation, the radiation sensitive regions and the damage physical mechanism and radiation sensitivity regions of PMOSFETs are given. This work provides the helpful theory guidance and technical supports for the radiation hardening of the nano-devices used in the radiation environments.