CMOSVLSI电路最大功耗估计

最大功耗分析对于设计高可靠性的VLSI芯片是非常重要的.由于电路功耗强依赖于其输入模式,对有大量管脚的CMOS组合或时序电路,不能采用穷举搜索.本文用遗传算法来选择具有高功耗的输入及内部状态模型,在逻辑仿真基础上实现CMOS电路的最大功耗估算.同时用逻辑仿真的统计方法来衡量获得最大功耗的质量.基于ISCAS85和ISCAS89基准电路的仿真表明,新方法在大规模门数时具有明显的优势,估算精度较高.而且新方法的计算时间基本上是电路逻辑门的线性关系.

Estimation of Maximum Power Dissipation of CMOS VLSI

Estimation of maximum power dissipation is important in designing highly reliable VLSI systems.However,maximum power estimation for CMOS circuits is essentially a combination optimization problem,which has exponential complexity in the worst case.In this paper,we propose a novel approach to obtain a lower bound of the maximum power dissipation using Genetic Algorithm (GA).Experiments with ISCAS 85 and ISCAS 89 benchmark circuits show that our approach generates the lower bound with the quality which cannot be achieved using simulation based techniques.In addition,a statistics based technique is realized to serve as a comparison version for our GA approach and to generate a metric to measure the equality of a lower bound from a statistical point of view.