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随机测试程序生成器研究
引用本文:刘志强,汪东升,郑纬民.随机测试程序生成器研究[J].计算机工程与设计,2005,26(2):281-284.
作者姓名:刘志强  汪东升  郑纬民
作者单位:清华大学,计算机系高性能计算研究所,北京,100084;清华大学,计算机系高性能计算研究所,北京,100084;清华大学,计算机系高性能计算研究所,北京,100084
基金项目:国家863高技术计划基金项目(2002AA1Z030)。
摘    要:随机测试是微处理器设计过程的重要环节,按照一定原则生成的随机指令序列,能够构造出指令组合的各种情况,达到比较好的测试强度和较高的覆盖率。介绍了一种基于模拟器的动态随机测试程序生成器的实现机制,此生成器用多个状态机来抽象整个被测处理器的可能行为,具有简单和高效的特点。给出了测试的统计数据。随机测试生成器对清华大学具有自主知识产权的微处理器的测试过程中取得了良好的测试效果。

关 键 词:有限状态机  指令树  模拟系统  微处理器
文章编号:1000-7024(2005)02-0281-04

Random test program generator for microprocessor verification
LIU Zhi-qiang,WANG Dong-sheng,ZHENG Wei-min.Random test program generator for microprocessor verification[J].Computer Engineering and Design,2005,26(2):281-284.
Authors:LIU Zhi-qiang  WANG Dong-sheng  ZHENG Wei-min
Abstract:Random test program generator (RTPG) is an important tool used in the test phase of the microprocessor design and implementation. According to some principles it randomly generates sequences of instructions. Thus it can construct interesting cases that are hard to be produced by other methods. Also, it brings out good testing intensity and high rate of coverage. A system for automatic simulation and verification of pipelined microprocessors is presented. In this system, multiple FSMs (finite-state-machine) are used to simulate the behavior of the whole processor. This method has made the system simple and efficient. Some statistical test data are given. The system has an encouraging result in the simulation and verification of the microprocessor developed by Tsinghua University.
Keywords:finite state machine (FSM)  instruction tree  simulation system  microprocessor
本文献已被 CNKI 维普 万方数据 等数据库收录!
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