微处理器功能验证的模拟加速方法

复杂微处理器的功能验证是当前主要的设计瓶颈．为提高验证效率，提出了自验证和混合模型模拟两种模拟加速方法．前者通过实现验证流程的自动化来提高验证效率，其有效性正比于激励空间的规模，反比于单个向量的平均模拟时间；后者则通过模拟不同抽象层次子模块模型组成的系统，将全芯片网表的验证时间从子模块数的指数关系降低到线性关系．该方法的有效性和可行性在32位处理器的设计实践中得到了验证．

Simulation Acceleration for Functional Verification of Microprocessor

Functional verification of complex microprocessor has now been a major bottleneck faced by design communities. To improve the efficiency of functional verification, this paper presents two efficient acceleration techniques: self-verification and co-simulation of mixed model. The former achieves the improvement of verification efficiency by automating the whole verification process over the vector space, and its effect is directly proportional to the number of vectors in the vector space, while inversely proportional to the average vector size. By simulating the system made up of modules at different abstract levels, the second method can reduce the time required to simulate full-chip netlist from exponential to linear relation with the number of integral modules. The validity of the proposed framework has been testified in the verification practice of a 32-bit high-end processor.