等精度数字转速表的VHDL设计

采用VHDL设计了基于等精度测量原理测量物体转速的数字电路,在闸门时间内的总误差时间只有1/fCLK,且在整个量程中具有相同的测量精度,克服了传统转速表在标称测量范围内,对应不同的转速具有不同的测量误差这一弊病.闸门信号采用32位可预置定时器,使电路在应用设计中更为便捷.采用了特殊的去噪电路,使FIN信号在等于1期间,脉宽<10/fCLK的噪声信号不会对测量产生影响;给出了去噪电路、控制电路和等精度测量电路的VHDL代码.在fCLK=10MHz时,可测转速范围的理论值为0.14～16777215r/min.

Design of equal precision digital tachometer based on VHDL

In this paper,we used VHDL to design a digital circuit of measuring rotational speed based on the equal precision measurement principles.The overall error in gate time is as low as 1/fCLK seconds,and the same precision can be kept steadily in the whole measuring range.This overcomes the traditional disadvantages which has different measurement error due to using different speed to measure.Under the condition of gate signal coming from 32 bit presettable timer,it is more convenient in design of applied circuit.The noise signals which is less than 10/fCLK have no effect to the results of the measurements by employing a special noise removal circuit.A noise removal circuit,control circuit and the VHDL codes of the circuits are presented.When the fCLK equals to 10 MHz,the oretical range of the measuring is from 0.14 r/min to 16 777 215 r/min.