LSC87中嵌入式ROM内建自测试实现

LSC87芯片是与Intel8086配套使用的数值协处理器，体系结构复杂，有较大容量的嵌入式ROM存储器，考虑到与Intel8087的兼容性和管脚的限制，必须选择合适的可测性设计来提高芯片的可测性。文章研究了LSC87芯片中嵌入式ROM存储器电路的设计实现，然后提出了芯片中嵌入式ROM电路的内建自测试，着重介绍了内建自测试的设计与实现，并分析了采用内建自测试的误判概率，研究结果表明，文章进行的嵌入式ROM内建自测试仅仅增加了很少的芯片面积开销，获得了满意的故障覆盖率，大大提高了整个芯片的可测性。

Design of Built-in Self-Test for Embedded ROM in LSC87

The numeric coprocessor LSC87we developed is compatible w ith Intel8087.This chip has a complex architecture and the pins of the chip are limited,so proper Design for Testa-bility(DFT)approaches are necessary to improve the testability of the chip and decrease test complexity.This paper describes the implementations of several embedded read-only memories(ROM's)w ithin the data path of the chip.As Built-in Self-test(BIST)provides an att ractive solution for ROM's,this paper puts forward the BIST design and impleme ntation of ROM's.The study shows BIST for ROM's has high fault coverage,and small hardware overhead.