Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor |
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Authors: | Won-Ho Choi Jungwoo OhOok-Sang Yoo In-Shik HanMin-Ki Na Hyuk-Min KwonByung-Suk Park P Majhi H-H TsengR Jammy Hi-Deok Lee |
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Affiliation: | a SEMATECH, Austin, TX 78741, USA b Department of Electronics Engineering, Chungnam National University, Yusong-Gu, Daejeon 305-764, Republic of Korea c Intel assignee |
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Abstract: | Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs. |
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Keywords: | Ge epitaxy Ge pMOSFETs NBTI High-k metal gate |
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