基于Verilog-AMS的VCO噪声建模

压控振荡器(VCO)是锁相环(PLL)的关键部件,目前多数研究都着重于VCO的电路级设计。采用Verilog-AMS语言对VCO进行行为建模,同时加入噪声模型,行为级设计中体现噪声。对比有噪声和无噪声的VCO行为模型,利用Cadence Spectre仿真引擎对2个模型进行了验证,将内嵌VCO行为模型的PLL系统与电路级PLL系统做了对比分析,结论为添加噪声的VCO行为模型更准确,更接近晶体管级电路,对仿真的速度与精度做了较好的折中。

Modeling VCO with Noise Using Verilog- AMS

Voltage Control Oscillator(VCO) is a key component of Phase-Locked Loop(PLL).Most of the research confined to the transistor-level design and noise studies.In this paper,VCO behavioral model is designed with Verilog-AMS language and VCO noise is contained in this model.So the noise will be incarnated in the behavioral design,system simulation is closer to the real circuit.In addition,VCO model contained noise is compared with VCO model without noise model,and two models are simulated with Cadence Spectre in this paper.Adding noise VCO behavioral model is more accurate and closer to the transistor-level circuit.