高速SerDes电路中电荷泵锁相环的设计

面向高速串行接口应用，设计一款低噪声、快速锁定的高性能锁相环电路，作为5 Gbit· s-1数据率的SerDes发射芯片的时钟源。该设计通过锁存RESET方式增加延迟时间，以减小鉴频鉴相器的死区效应，降低锁相环整体电路的杂散；其压控振荡器采用4 bit二进制开关电容的方法，将输出频率划分为16个子频带，以获得较大的输出频率范围，同时又不增加压控振荡器的增益；在SMIC 55 nm工艺下完成锁相环电路版图设计，核心芯片面积为054 mm2。后仿真结果表明:输出频率覆盖46~56 GHz，1 MHz频偏处的相位噪声在-110 dBc·Hz-1 附近。测试结果显示，RMS 抖动和峰峰值抖动分别为287 ps和134 ps，整体电路功耗为37 mW。

Designing a Charge Pump Phase Locked Loop in High Speed SerDes Circuit

For high speed serial interface applications,a low noise,fast locking high performance phase locked loop PLL is designed as the clock source of the SerDes transmitter chip with a data rate of 5 Gbit·s-1.In this paper,the delay time is increased by latching the RESET method to reduce the dead zone effect of the phase frequency detector,thereby reducing the spurs of the overall circuit of the phase locked loop.The voltage controlled oscillator uses a 4 bit binary switched capacitor to divide the output frequency into 16 sub bands so that a larger output frequency range can be obtained without increasing the gain of the VCO.After that,the circuit simulation and layout design are completed under the SMIC 55 nm process,and the core chip area is 0.54 mm2.The post simulation results show that the output frequency covers 4.6~5.6 GHz,the phase noise at 1 MHz frequency deviation is around -110 dBc/Hz.The test results show that the RMS jitter and peak to peak jitter are 2.87 ps and 13.4 ps respectively,and the total circuit power consumption is 37 mW.