基于FPGA的数字下变频器的设计

采用软件无线电思想,设计和实现了基于FPGA的数字下变频器,应用于数字中频接收机中,主要完成信号的下变频、多速率抽取和滤波等功能。采用自上向下的模块化设计方法,将数字下变频的功能划分为不同的模块,通过VHDL语言和IP核设计各功能模块。通过ISE和Matlab工具对数字下变频器进行了仿真设计,在FPGA硬件平台上进行了测试验证,结果表明:数字下变频器稳定可靠、通用性强、灵活性高,满足数字中频接收机的设计要求。

Design of digital downconverter based on FPGA

The digital downconverter（DDC）based on FPGA was designed and implemented with the idea of software ra-dio. It is applied to the digital intermediate frequency receiver to complete the signal downconvertion,multi-rate decimation and filtering functions. The top-down modular design method is adopted to divide the DDC functions into different modules. All the function modules are designed with VHDL language and IP core. The simulation design of DDC is achieved with ISE and Matlab tools,and tested on the FPGA hardware platform. Performance testing results show that the DDC has high stability,high reliabili-ty,strong versatility and high flexibility,and can meet the design requirements of the digital intermediate frequency receiver.