| 流水线结构RS译码器的超大规模集成电路设计 |
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| 引用本文： | 季君,黄秋萍.流水线结构RS译码器的超大规模集成电路设计[J].江苏电器,2007(Z1). |
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| 作者姓名： | 季君 黄秋萍 |
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| 作者单位： | 苏州大学电子信息学院 江苏苏州215021 |
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| 摘 要： | RS码已经广泛地应用于通信系统、数字电视和计算机存储系统中,用来提高数据可靠性.以数字电视广播(DVB)标准中定义的RS(204,188)译码器为例,详细介绍了改进的欧几里德(ME)算法及以此算法为基础的RS译码器的超大规模集成电路VLSI实现,采用了流水线结构,对译码器的各个模块进行了分析和建模.通过对流程的仿真和综合验证,发现这些模块能较好的满足设计要求,能纠正不大于8个的误码.
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| 关 键 词： | RS译码器 流水线结构 VLSI建模 流水线结构 译码器 超大规模集成电路 集成电路设计 Decoder Pipeline Design 误码 发现 验证 综合 仿真 流程 建模 分析 模块 VLSI 算法 欧几里德 改进 |
VLSI Design of Pipeline Reed-Solomon Decoder |
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| Authors: | JI Jun HUANG Qiu-ping |
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| Abstract: | Reed-Solomon code has been widely used in communication systems, digital television and computer storage systems to enhance data reliability. This paper takes the Reed-Solomon (204,188) decoder which is defi ned in DVB standard for an example. The Modifi ed Euclidean (ME) algorithm and the VLSI implemented of Reed-Solomon decoder based on the algorithm are described in detail. The structure of decoder is pipeline. Modeling and analyzing some modules of the Reed-Solomon decoder. These modules afford satisfaction to the needs of the design and can correct the error codes less than 8 through the simulation and synthesis. |
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| Keywords: | Reed-Solomon decoder pipeline structure VLSI modeling |
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